Deadline: Sunday, May 8, 23:59
This is an individual project. This lab must be done on machines in the Asprey lab or machines in SP 309. Any clarifications and corrections to the assignment will be posted on the class website.
In this exercise, you will create a small C program that simulates cache behavior.
Download the task
Start destroying the labstart codefrom the class website and unzip that tar file to the directory where you plan to do your work.
CDcs224wget https://cs224.cs.vassar.edu/assignments/cachelab.tartar xvf cachelab.tarCDcache lab
You do all your work in this directory. You are going to change the file:
csim.c. Enter the following command to compile this file and build the simulator:
In this exercise, you will implement a cache simulator.
Reference trace files
songsthe subfolder contains the collectiontracking reference fileswhich we will use to evaluate the accuracy of the cache simulator you have written. Trace files are generated by a Linux program called
election door. For example, writing
valgrind --log-fd=1-- tool=lakej -v --trag-mem=da ls
on the command line runs an executable program
ls, saves a trace of each of its memory accesses in the order they occur and prints them further
election doormemory traces have the following form:
i 0400d7d4,8M 0421c7f0,4L 04f6b868,8S7ff0005c8,8
Each line indicates one or two memory accesses. The format of each line is
[space] edit address, size
operationthe field indicates the type of memory access:
Windicates instruction load,
Sdata storage and
Mdata modification (i.e. data loading followed by data storage). There is never room for everyone
W. There will always be a place for everyone
Addressfield specifies a 64-bit hexadecimal memory address. The
matthe field specifies the number of bytes the operation can access.
Writing a cache simulator
You are about to write a cache simulator
csim.cit lasts a
election doormemory trace as input, simulates cache hit/miss behavior on that trace, and returns the total number of hits, misses, and rejects.
We have provided you with a reference binary executable of the caching simulator called
csim-refwhich simulates cache behavior of arbitrary size and associativity on a
election doortrace file. Uses the LRU replacement rule (least used) when selecting the cache rule to delete.
The credential simulator uses the following command-line arguments:
-H: Guide flag that prints usage information
-w: Extended tag displaying tracking information
-S: Number of index bits set (S = 2Sis the number of sets)
-MI: Associativity (number of rows in a set)
-B: Number of block bits (B = 2Bis the block size)
election doornumber to repeat
Command line arguments are based on the format (
B) from page 617 of the CS:APP3e manual. For example:
linux> ./csim-ref -s2-MI1-B4-t trace/t2. tracehits: 4 misses: 5 droppings: 3
The same example in verbose mode:
linux> ./csim-ref -v -s2-MI1-B4-t trace/t2. traceL 10,1Hits: 0, Misses: 1, Throws:0S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:0 LRU:1S:2 L:0 V:0 T:0 LRU:0S:3 L:0 V:0 T:0 LRU:0M 20,1Hits: 1, misses: 2, accidents:0S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:0 LRU:1S:2 L:0 V:1 T:0 LRU:2S:3 L:0 V:0 T:0 LRU:0L 22,1Hits: 2, Misses: 2, Accidents:0S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:0 LRU:1S:2 L:0 V:1 T:0 LRU:3S:3 L:0 V:0 T:0 LRU:0S 18,1Hits: 3, misses: 2, accidents:0S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:0 LRU:4S:2 L:0 V:1 T:0 LRU:3S:3 L:0 V:0 T:0 LRU:0L 110,1Hits: 3, Misses: 3, Throws:1S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:4 LRU:5S:2 L:0 V:1 T:0 LRU:3S:3 L:0 V:0 T:0 LRU:0L 210,1Hits: 3, Misses: 4, Accidents:2S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:8 LRU:6S:2 L:0 V:1 T:0 LRU:3S:3 L:0 V:0 T:0 LRU:0M 12,1Hits: 4, Misses: 5, Accidents:3S:0 L:0 V:0 T:0 LRU:0S:1 L:0 V:1 T:0 LRU:7S:2 L:0 V:1 T:0 LRU:3S:3 L:0 V:0 T:0 LRU:0hits: 4 misses: 5 droppings: 3
Your job is to fill it
csim.cso that it takes the same command line arguments and produces identical output as the reference simulator.
Please enter your name in the header comment
csim.cFile must be submitted without warning to receive credit.
Your simulator should run fine randomly
B. This means that memory is used to store simulator data structures
Pan Mallokfor information about this feature.
When caching a row, if there is a blank row in the cache for the resource, you can do thismoraput it in the first free row. This is what the benchmark simulator does, and you should match this behavior to compare your cache with the benchmark simulator.
In this lab, we are only interested in data cache performance, so your simulator should ignore all instruction cache accesses (lines starting with
W). Remember it
election dooralways bet
Win the first column (no spaces in front), i.e
Sin the second column (with a space at the beginning). This can help you analyze the trace.
To get points for this lab, you need to call a function
drukujSamenvatting, with the total number of hits, misses and falls, at the end of yours
printSummary(hit_count, miss_count, ontruiming_count);
For the purposes of this lab, assume that memory accesses are properly aligned so that a single memory access never crosses block boundaries. This assumption allows you to ignore request sizes in
This section describes how your work will be assessed. The full score of this lab is 100 points:
- Symulator Ispravnost: 81 bod
print cachework efficiency: 10 points
- Style: 9 points
We will run your cache simulator using various parameters and cache traces. There are eight test cases, each worth 9 points, except for the last case, which is worth 18 points:
linux> ./csim -s2-MI1-B4-t trace/t1. tracelinux> ./csim -s4-MI2-B4-t trace/t2. tracelinux> ./csim -s1-MI1-B1-t tragovi/t3.tragovilinux> ./csim -s2-MI1-B3-t tragovi/t4.tragovilinux> ./csim -s2-MI2-B3-t tragovi/t4.tragovilinux> ./csim -s2-MI4-B3-t tragovi/t4.tragovilinux> ./csim -s5-MI1-B5-t tragovi/t4.tragovilinux> ./csim -s5-MI1-B5-t traces/t5.traces
You can use the reference simulator
csim-refto get the correct answer for each of these test cases. When debugging use
-wthe option of a detailed report on each hit and miss.
For each test case, logging the exact number of hits, misses, and rejects in the cache gives full credit to that test case. Each reported hit, miss, and deletion is worth 1/3 of the credit for that test case. This means that if a given test case is worth 9 points and your simulator reports the correct number of hits and misses but reports the wrong number of droppings, you will score 6 points.
In addition to correctness, there are 10 points for completing one
print cachefunction. This function prints the entire contents of the cache. This can be very useful when debugging your code. Called when the simulator starts
Judging by the style
There are 9 points for coding style. I will assign them manually. I'm looking for code that is well documented with comments and easy to understand.
job at laboratory
We have provided you with an automatic grading program called
body clipwhich tests the validity of the cache simulator against reference traces. Remember to compile the simulator before running the test:
Linux > createlinux> ./test-csimYour simulator Reference simulatorsteering(s,E,b)Hits misses evictions hits misses evictions 0 (2,1,4) 0 0 0 2 3 1traces/t1.spores 0 (4,2,4) 0 0 0 4 5 2traces/t2.spores 0 (1,1,1) 0 0 0 9 8 6tragovi/t3.tragovi 0 (2,1,3) 0 0 0 167 71 67tragovi/t4.tragovi 0 (2,2,3) 0 0 0 201 37 29tragovi/t4.tragovi 0 (2,4,3) 0 0 0 212 26 10tragovi/t4.tragovi 3 (5,1,5) 0 0 0 231 7 0tragovi/t4.tragovi 0 (5,1,5) 0 0 0 265189 21775 21743traces/t5.spores 3TEST_CSIM_RESULTS=3
For each test, it shows the number of points scored, cache parameters, input trace file, and a comparison of simulator and reference simulator results.
Here are some tips and suggestions for working in the lab:
- Do some initial debugging on small traces like
- The reference simulator is optional
-wan argument that provides verbose output, displays the hits, misses, and discards that occur as a result of each memory access, and also displays the contents of the cache.Implement this feature first!Helps with debugging by allowing simulator behavior to be compared directly with the reference simulator in reference trace files.
- Each data load (L) or save (S) operation may result in a maximum of one cache failure. A data change operation (M) is treated as a load followed by a write to the same address. Therefore, an M operation may result in two cache hits, or a miss and a hit, and a possible rejection.
- Since you don't know the size of the cache at compile time (because it depends on the options the user runs the program with), you have to dynamically map all the data structures you use
malloc()call the library. We've implemented it for you, but it's worth reviewing the code to make sure you understand how it works.
Submit your work
Submit a gift