Blog | Generate Verilog code with Simulink | MATLAB helper (2023)

What is a VLSI?

VLSI is also referred to as very large integration. IT is the process of creating a complex circuit by combining and combining multiple transistors into a single silicon semiconductor. AS software development requires programming languages ​​that act as a bridge between the human-computer interface; Similarly, in VLSI there is a language called Verilog which is used to create complex circuits by coding.

Semiconductor chip

Introduction to Verilog

Verilog is a hardware description language (HDI) standardized as IEEE 1364. It is used to model electronic systems. It is mainly used in the verification and optimization of digital circuit designs at the register transfer abstraction level. It also monitors analog circuits, RF ICs, and mixed signal circuits.

The Verilog language supports design at multiple levels of abstraction. The three main ones are:

• Behavior level
• Data flow speed
• Door level

Behavior Level:

• It provides the highest level of abstraction that Verilog HDL offers.
• The module can be implemented using the desired design algorithm without worrying about hardware implementation details.
• Specifies the circuit in terms of its expected behavior.
• This is the closest to describing circuit functionality in natural language, but also the most difficult to synthesize.

Data flow level:

• At this level, the module is designed by specifying the data flow.
• By looking at this project, you can understand how data flows between hardware registers and how data is handled in the project.
• This style is similar to logic equations. The specification consists of expressions consisting of input signals and assigned to outputs. In most cases, this approach can be easily translated into a structure and implemented.

door level:

• The module is used in logic gates and connections between these gates.
• It looks like a schematic drawing with components connected to signals.
• Since logic gates are the most common component, Verilog has a predefined set of logic gates called primitives. Any digital circuit can be built with these primitives.

Lexical tokens:

Verilog source text files are a channel for lexical tokens. It consists of one or more characters, and each individual character can only be found in one token. Typical tokens used by Verilog HDL are similar to those used in the C programming language.

A programming language. Verilog is case-sensitive. All keywords are lowercase.

Comments:

There are two ways to present comments:

• Single-line comments start with a // token and end with a character

give. Eg: //this is one-line syntax

• Multi-line comments start with /* and end with */ E.g. /*this is multi-line syntax/

numbers:

• The number can be specified in binary, octal, decimal, or hexadecimal format.
• Negative numbers are represented in 2's complement numbers.
• Verilog accepts integers, real numbers, and signed and unsigned numbers.
• The syntax is given by-
• A measure or an immeasurable number can be represented by, aindicates whether it is a binary, octal, hexadecimal or decimal number.

Identification:

An identifier is a name that defines an object, such as a function, module, or register. Identifiers must start with alphabetic characters or underscores. For example, A_Z, a_z. Identifiers consist of letters, numbers, underscores, and $ signs. Their size can be up to 1024 characters.

Operators:

Operators are special characters used to set conditions or manipulate variables. One, two, and sometimes three characters are used to perform variable operations. Example: >, +, ~

Verilog keywords:

Some words have a special meaning in Verilog and are called Verilog keywords. For example, assign case, while, wire, reg i, or, nand and module. They cannot be used as a means of identification. Verilog keywords also include compiler directives and system tasks and functions.

Basic elements of vrata:

Verilog uses simple logic gates that use one output and multiple inputs; GATE uses one of the keywords en, nand, or, nor, xor, xnor for use in Verilog for N number of inputs and I outputs.

Benefits of Verilog:

• Abstraction
• Competition
• Supplier neutrality
• Reuse
• Scalability

Half allowance:

The purpose of the addition circuit is to add two numbers. There are two inputs, augment and addend, for which two outputs are generated: sum and carry. It consists of two gates, an XOR gate and an AND gate. The XOR gate is responsible for obtaining the sum, and the AND gate ensures the transfer of the input data.

Truth table:

Krug Simulink:

half adder

Full number:

In the full adder circuit, 3 one-bit numbers are added. Two of the three bits serve as the operand, while the last bit is called the carry bit and gives a two-bit result.

Truth table:

Krug Simulink:

Full passerby

You can read more about half adder and full adderHere. You can see the difference between Half Adder and Full Adder along with the VHDL codeHere.

Decoder:

Adecoderis a multi-input and multi-output logic circuit that converts coded inputs to coded outputs where the inputs and outputs are different, such as in n-to-2n and binary-decimal decoders. Decoding is essential for applications such as data multiplexing, memory address decoding, and 7-segment display. The best example of a decoder circuit would be an AND gate, because when both inputs are "High", the output of the gate goes "High". NAND gates are an alternative to AND gates and the output will only be "Low" (0) when all inputs are "High". This output is called "active low output".

Truth table:

Krug Simulink:

Decoder

Multiplexes:

Amultiplexis a device with multiple inputs and a single line output. The selected lines determine which input is connected to which output and increase the amount of data sent over the network at any given time. It is also called a data selector.

Truth table:

Krug Simulink:

Multiplexes

VLSI Verilog code generation with Simulink:

After creating an assembly in Simulink, you need to develop a subsystem. To create a subsystem, drag and select a part of the circuit consisting only of logic gates. After creating the subsystem, we need to go to the "Applications" section and select HDL Coder from the list. The HDL Coder interface will open and we must go to the HDL code generation settings which has the following interface:

HDL encoder interface

We just need to generate the HDL code for "Subsystem" and we will select it. We can select the language in Verilog or VHDL; in this case we preferred it to be Verilog.

You can relateImplement additional circuits in Simulinkfree lesson with usOsnove SimulinkaA course to understand the implementation of circuits in Simulink.

Finally, we select the destination folder path and click "Generate". Once we've done that, we can go back to MATLAB and view our file by clicking on the ".v" file, as shown below:

HDL code generation result

Application:

In this blog, we learned what VLSI is and what are the terms associated with it. Verilog is a machine language used to help computers understand how to create complex circuits using logic gates.

We built a series of circuits using logic gates in Simulink, developed subsystems, and then generated Verilog code for various circuits using an HDL encoder.